#
# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

#Create the project in the output directory
#create_project project_1 -force  -part xcvc1902-vsva2197-2MP-e-S
set_part xcvc1902-vsva2197-2MP-e-S
#Set the board part
set_property board_part xilinx.com:vck190:part0:3.2 [current_project]

#####Read all sources for building the project#####

#Generate the system BD that has only CIPS and DDR NOCs
read_bd ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/bd/design_1/design_1.bd

#Read the RTL files that has XPM NMUs and NSUs instantiated along with traffic generators and BRAM 
read_verilog {../sources/rtl/axis_MxN_top.v ../sources/rtl/design_1_wrapper.v ../sources/rtl/pl_master_to_cips.v ../sources/rtl/pl_master_to_ddr.v ../sources/rtl/pl_master_to_pl_slave.v ../sources/rtl/pl_slave_from_cips.v ../sources/rtl/pl_to_pl_master.v ../sources/rtl/pl_to_pl_slave.v ../sources/rtl/validate_ip_M_AXIS.v ../sources/rtl/validate_ip_S_AXIS.v}

#Add generated XCI from golden project
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axi_bram_ctrl_pl_slave_from_pl_master/axi_bram_ctrl_pl_slave_from_pl_master.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axi_bram_ctrl_pl_slave_from_ps/axi_bram_ctrl_pl_slave_from_ps.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axis_vio_pl_master_to_ddr/axis_vio_pl_master_to_ddr.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axis_vio_pl_master_to_pl_slave/axis_vio_pl_master_to_pl_slave.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axis_vio_pl_master_to_ps/axis_vio_pl_master_to_ps.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axis_MxN_vio/axis_MxN_vio.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axi_tg_pl_to_pl/axi_tg_pl_to_pl.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axi_tg_pl_to_ps/axi_tg_pl_to_ps.xci
read_ip ../sources/vivado_prj_xci_bd/vivado_prj_xci_bd.srcs/sources_1/ip/axi_tg_pl_master_to_ddr/axi_tg_pl_master_to_ddr.xci

#Read the XDC files for creating NoC connection, setting its QoS settings and the aperture of XPM NSUs. 
read_xdc ../sources/xdc/noc_constraints.xdc

#Read the XDC files that has constraints for creating ILAs and for connecting them to debug hub in the design. This constraint is auto-generated by the tool based on "Set up Debug" flow.
read_xdc ../sources/xdc/design_1_wrapper_debug.xdc

#####Set the USED_IN {synthesis_pre} for NoC constraints#####
set_property USED_IN {synthesis_pre} [get_files noc_constraints.xdc]

#####Generate all targets : XCI/BD######
#BD and XCI are already generated and synthesized in golden project. No need to generate again 

##Launch Synthesis/Implementation and WDI. 
#start_gui
synth_design -top design_1_wrapper -part xcvc1902-vsva2197-2MP-e-S
write_checkpoint -force outputs/dcps/post_synth.dcp
